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<div class="header">
  <div class="headertitle"><div class="title">SPI_TypeDef Struct Reference<div class="ingroups"><a class="el" href="group___c_m_s_i_s___device.html">CMSIS_Device</a> &raquo; <a class="el" href="group__stm32h723xx.html">Stm32h723xx</a> &raquo; <a class="el" href="group___peripheral__registers__structures.html">Peripheral_registers_structures</a></div></div></div>
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<p>Serial Peripheral Interface.  
 <a href="#details">More...</a></p>

<p><code>#include &lt;<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a>&gt;</code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-pub-attribs" class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
Public Attributes</h2></td></tr>
<tr class="memitem:a6ecd5cb63b85c381bd67dc90dd4f573a" id="r_a6ecd5cb63b85c381bd67dc90dd4f573a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a6ecd5cb63b85c381bd67dc90dd4f573a">CR1</a></td></tr>
<tr class="memitem:a38cb89a872e456e6ecd29b6c71d85600" id="r_a38cb89a872e456e6ecd29b6c71d85600"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a38cb89a872e456e6ecd29b6c71d85600">CR2</a></td></tr>
<tr class="memitem:a1fd1ba3ba655258308d26cdcfaf4bc5e" id="r_a1fd1ba3ba655258308d26cdcfaf4bc5e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a1fd1ba3ba655258308d26cdcfaf4bc5e">CFG1</a></td></tr>
<tr class="memitem:ab40edb77993e6f1343c5999f62e5a157" id="r_ab40edb77993e6f1343c5999f62e5a157"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ab40edb77993e6f1343c5999f62e5a157">CFG2</a></td></tr>
<tr class="memitem:add74ef50f1985dc0afe8af8226d84051" id="r_add74ef50f1985dc0afe8af8226d84051"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#add74ef50f1985dc0afe8af8226d84051">IER</a></td></tr>
<tr class="memitem:a33f3dd6a505d06fe6c466b63be451891" id="r_a33f3dd6a505d06fe6c466b63be451891"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a33f3dd6a505d06fe6c466b63be451891">SR</a></td></tr>
<tr class="memitem:ada4f3c195a523945fca842215c67d8d5" id="r_ada4f3c195a523945fca842215c67d8d5"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ada4f3c195a523945fca842215c67d8d5">IFCR</a></td></tr>
<tr class="memitem:a2e297cd0cbca5b9878dab319aee83ae5" id="r_a2e297cd0cbca5b9878dab319aee83ae5"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a2e297cd0cbca5b9878dab319aee83ae5">RESERVED0</a></td></tr>
<tr class="memitem:a519806144e513633e6a0093fd554756f" id="r_a519806144e513633e6a0093fd554756f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a519806144e513633e6a0093fd554756f">TXDR</a></td></tr>
<tr class="memitem:a6e739471dd1c66b23dd856f4391860ab" id="r_a6e739471dd1c66b23dd856f4391860ab"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a6e739471dd1c66b23dd856f4391860ab">RESERVED1</a> [3]</td></tr>
<tr class="memitem:a0339afbc47839f09598f7fb09c242b09" id="r_a0339afbc47839f09598f7fb09c242b09"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a0339afbc47839f09598f7fb09c242b09">RXDR</a></td></tr>
<tr class="memitem:a2021528927d75d06c03dcedb9fc36d51" id="r_a2021528927d75d06c03dcedb9fc36d51"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a2021528927d75d06c03dcedb9fc36d51">RESERVED2</a> [3]</td></tr>
<tr class="memitem:a03d6f39b695fb8e316e97c8a089cd46b" id="r_a03d6f39b695fb8e316e97c8a089cd46b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a03d6f39b695fb8e316e97c8a089cd46b">CRCPOLY</a></td></tr>
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<tr class="memitem:a189a6e7526779ec981cd411bc4bd3a51" id="r_a189a6e7526779ec981cd411bc4bd3a51"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a189a6e7526779ec981cd411bc4bd3a51">UDRDR</a></td></tr>
<tr class="memitem:a4a1547c0ed26f31108910c35d2876b83" id="r_a4a1547c0ed26f31108910c35d2876b83"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a4a1547c0ed26f31108910c35d2876b83">I2SCFGR</a></td></tr>
</table>
<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Serial Peripheral Interface. </p>
</div><a name="doc-variable-members" id="doc-variable-members"></a><h2 id="header-doc-variable-members" class="groupheader">Member Data Documentation</h2>
<a id="a1fd1ba3ba655258308d26cdcfaf4bc5e" name="a1fd1ba3ba655258308d26cdcfaf4bc5e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a1fd1ba3ba655258308d26cdcfaf4bc5e">&#9670;&#160;</a></span>CFG1</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SPI_TypeDef::CFG1</td>
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<p>SPI Configuration register 1, Address offset: 0x08 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ab40edb77993e6f1343c5999f62e5a157">&#9670;&#160;</a></span>CFG2</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SPI_TypeDef::CFG2</td>
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<p>SPI Configuration register 2, Address offset: 0x0C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a6ecd5cb63b85c381bd67dc90dd4f573a">&#9670;&#160;</a></span>CR1</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SPI_TypeDef::CR1</td>
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<p>SPI/I2S Control register 1, Address offset: 0x00 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a38cb89a872e456e6ecd29b6c71d85600">&#9670;&#160;</a></span>CR2</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SPI_TypeDef::CR2</td>
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<p>SPI Control register 2, Address offset: 0x04 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a03d6f39b695fb8e316e97c8a089cd46b">&#9670;&#160;</a></span>CRCPOLY</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SPI_TypeDef::CRCPOLY</td>
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<p>SPI CRC Polynomial register, Address offset: 0x40 </p>

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<p>I2S Configuration register, Address offset: 0x50 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#add74ef50f1985dc0afe8af8226d84051">&#9670;&#160;</a></span>IER</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SPI_TypeDef::IER</td>
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<p>SPI/I2S Interrupt Enable register, Address offset: 0x10 </p>

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<p>SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 </p>

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<p>Reserved, 0x1C </p>

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<p>Reserved, 0x24-0x2C </p>

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<p>Reserved, 0x34-0x3C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aa3d580e3aa375dd3e6c1a3331e819300">&#9670;&#160;</a></span>RXCRC</h2>

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<p>SPI Receiver CRC register, Address offset: 0x48 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a0339afbc47839f09598f7fb09c242b09">&#9670;&#160;</a></span>RXDR</h2>

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<p>SPI/I2S Receive data register, Address offset: 0x30 </p>

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<p>SPI/I2S Status register, Address offset: 0x14 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a9fffd568c7ff1da72b24c45c62566abd">&#9670;&#160;</a></span>TXCRC</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SPI_TypeDef::TXCRC</td>
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<p>SPI Transmitter CRC register, Address offset: 0x44 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a519806144e513633e6a0093fd554756f">&#9670;&#160;</a></span>TXDR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SPI_TypeDef::TXDR</td>
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<p>SPI/I2S Transmit data register, Address offset: 0x20 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a189a6e7526779ec981cd411bc4bd3a51">&#9670;&#160;</a></span>UDRDR</h2>

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<p>SPI Underrun data register, Address offset: 0x4C </p>

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<hr/>The documentation for this struct was generated from the following file:<ul>
<li>C:/Users/ASUS/Desktop/dm-ctrlH7-balance-9025test/Drivers/CMSIS/Device/ST/STM32H7xx/Include/<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a></li>
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